This invention relates to an address translation device for use in combination with a main memory of an information processing system in translating an input virtual address into an output real address.
In an information processing system, pipeline control is often adopted in order to process a sequence of instructions at a high speed. To this end, a host device, such as an execution processing unit, of the information processing system carries out prefetch or lookahead of instructions from a main memory prior to execution of the prefetched instruction. This shows that the main memory is accessed by the execution processing unit. If the prefetched instruction is either a store instruction or a load instruction, calculation is preliminarily carried out to get an address in the main memory prior to storage or loading. If the prefetched instruction is an operation instruction, one or a plurality of operands are read out of the main memory prior to execution of the operation instruction. If the prefetched instruction is a conditional branch (branch on condition) instruction indicative of a branch on condition, at least one instruction is prefetched on a branch prior to execution of the conditional branch instruction.
A virtual address is produced from the execution processing unit on accessing the main memory and must, therefore, be translated into a corresponding real address of the main memory. In other words, address translation of a virtual address into a real address is indispensable for such an information processing system and may be made by looking up an address translation table stored in the main memory. The address translation table is loaded with a memory presence bit indicative of presence or absence of data for a real address in the main memory in correspondence to the virtual address. It is, however, unavoidable that the address translation is carried out at a low speed. On the other hand, the address translation table must be looked up each time that the address translation is necessary. Therefore, such a table look-up results in an objectionably slow execution rate, despite the pipeline control.
In order to make the execution rate faster, an address translation device is used to carry out address translation of a virtual address into a real address at a high speed. A conventional address translation device comprises an address translation buffer which may be called a translation lookaside buffer (TLB) and which stores or memorizes a predetermined number of entries in relation to virtual addresses already issued from the execution processing unit. More specifically, the address translation buffer is for memorizing a plurality of buffer virtual addresses and a plurality of buffer real addresses corresponding to the respective buffer virtual addresses. The address translation buffer may be loaded with a validity bit representative of either validity or invalidity of each entry. Responsive to a predetermined part of a device input signal which represents the input virtual address, the address translation buffer produces a buffer output signal representative of a particular one of the buffer virtual addresses and a specific validity bit corresponding to the particular buffer virtual address. Although only a part of the device input signal is used, the particular one of the buffer virtual addresses corresponds to the input virtual address. The buffer output signal further represents a particular one of the buffer real addresses that corresponds to the particular buffer virtual address. The conventional address translation device comprises a comparator for comparing the input virtual address with the particular buffer virtual address.
With this structure, the address translation buffer is at first looked up by the input virtual address and quickly carries out address translation of the input virtual address into an output real address as long as the output real address is memorized in correspondence to the input virtual address in question, namely, when the input virtual address coincides with the particular buffer virtual address and, furthermore, when the specific validity bit indicates validity. Stated otherwise, the address translation table of the main memory is accessed only in the absence of any entry corresponding to the input virtual address in question, namely, either when the input virtual address and the particular buffer virtual address do not coincide with each other or when the specific validity bit indicates invalidity. If a specific one of the presence bits that corresponds to the input virtual address indicates an absence, the input virtual address and the corresponding real address are not stored into the address translation buffer.
Under the circumstances, the input virtual address and the corresponding real address are stored in the address translation buffer as the particular buffer virtual address and the particular buffer real address if the specific presence bit indicates only a presence. Simultaneously, the address translation buffer is loaded with the validity bit representative of validity of the particular buffer virtual address. Thereafter, the input virtual address in question is translated into the corresponding output real address by the address translation buffer at a high speed.
The above technique, which is known as a conventional technique, is disclosed in the IBM document SA22.7200-0 "IBM Enterprise Systems Architecture/370 Principles of Operation", pages 3-31 through 3-32.
It will now be assumed that the conditional branch instruction is prefetched as a prefetched instruction in the execution processing unit. Until it is not decided whether or not a branch condition of the conditional branch instruction is realized, the execution processing unit usually carries out prefetch of two instructions from the main memory that are memorized at two real addresses in correspondence to two branch destination virtual addresses indicated by the prefetched conditional branch instruction. After it is decided whether or not the branch condition is realized, the execution processing unit throws away one of the two instructions as a discarded instruction. However, such a prefetch operation can not always be carried out. This is because one or both of the two real addresses in question are not always present in the main memory. In this case, the execution processing unit can not carry out the prefetch operation even by an access to the address translation table in the main memory.
It will now be assumed that the execution processing unit carries out a program including a loop which should be repeated a predetermined number of times. It will furthermore be assumed that the loop comprises a conditional branch instruction and that the discarded instruction is stored in a real address which is absent in the main memory. In this event, the execution processing unit must access the address translation table whenever the prefetch operation is carried out on the conditional branch instruction. The address translation table is accessed a plurality of times which are equal in number to the predetermined number.
Accordingly, the information processing system including the conventional address translation device is disadvantageous in that an address translation operation undesirably wastes time. That is, the conventional address translation device results in degradation of performance of the information processing system.